There is a vertical metal oxide semiconductor field effect transistor (MOSFET) in which a p type (or n type) semiconductor layer is embedded in an n type (or p type) semiconductor layer. The vertical MOSFET can have a super junction structure (a “SJ structure”) in which n type and p type regions are alternately arranged. In a semiconductor device for power control such an arrangement provides a high breakdown voltage and a low ON resistance. In the SJ structure, the amount of n type impurities included in the n type region is equal to the amount of p type impurities included in the p type region, this arrangement of balanced n and p type impurities, in effect, simulates or behaves in relevant aspect as a non-doped region and a high breakdown voltage is thus achieved. At the same time, current in the device can flow through a region having high impurity concentration, and thus it is still possible to achieve a low ON resistance.
As a method for forming the SJ structure, for example, there is a method of forming trenches in an n type semiconductor layer and filling the trenches with a p type semiconductor material. However, in this method, a hollow portion (empty hole, void) may easily be formed inside a p type semiconductor material.